Organisation of a Computer PDF, Free Study Notes & Live Quiz

1. Which of the following is NOT one of the five basic functional units of a computer?

Arithmetic Logic Unit
Control Unit
Compiler Unit
Input Unit

2. In a Von Neumann architecture, instructions and data are stored in:

Separate instruction and data memories
The same unified memory
Registers only
Cache only

3. The ‘Von Neumann bottleneck’ refers to:

Limited register count
Slow ALU operations
The single bus between CPU and memory limiting throughput
Inability to support floating point

4. Harvard Architecture is commonly used in:

Desktop personal computers
Mainframe systems
Digital Signal Processors (DSPs) and microcontrollers
Cloud servers

5. Which register always holds the address of the NEXT instruction to be fetched?

Instruction Register (IR)
Program Counter (PC)
Memory Address Register (MAR)
Accumulator (ACC)

6. The Memory Buffer Register (MBR) is used to:

Hold the opcode of the current instruction
Temporarily hold data being transferred to/from memory
Store the address of a memory operand
Count the number of memory accesses

7. What is the function of the Accumulator register?

Store the base address for indexed addressing
Store the return address for subroutine calls
Store the intermediate and final results of ALU operations
Hold the current value of the stack pointer

8. Which flag in the Status Register is set when the result of an ALU operation is zero?

Sign flag
Carry flag
Overflow flag
Zero flag

9. In the fetch-decode-execute cycle, what happens immediately after the instruction is fetched?

The instruction is executed
The instruction is decoded
The result is written back to memory
The PC is decremented

10. During the Fetch stage of the instruction cycle, which two registers are primarily involved?

ACC and IR
PC and MAR
SP and MBR
GPR and PSW

11. In which addressing mode is the operand directly specified as part of the instruction itself?

Direct Mode
Indirect Mode
Immediate Mode
Register Mode

12. Which addressing mode provides the FASTEST operand access?

Indirect Mode
Direct Mode
Immediate Mode
Register Mode

13. In indirect addressing mode, the instruction contains:

The operand value directly
The address of the operand
The address of the address of the operand
An offset to be added to the PC

14. Indexed addressing mode is most commonly used for:

Calling subroutines
Accessing elements of an array
Fetching the next sequential instruction
Handling interrupt vectors

15. Relative addressing mode computes the effective address as:

PC + Displacement
Base Register + Displacement
Index Register + Constant
Stack Pointer + Offset

16. RISC architecture is characterized by:

Complex variable-length instructions, many memory addressing modes
Simple fixed-length instructions, load-store design, large register file
Microprogrammed control unit, few registers
Memory-to-memory operations, variable execution cycles

17. Which of the following is an example of a CISC architecture?

ARM Cortex-A series
MIPS R3000
Intel x86
SPARC V9

18. VLIW (Very Long Instruction Word) architecture is designed to:

Execute one operation per clock cycle by keeping instructions short
Issue multiple operations in a single long instruction word simultaneously
Reduce instruction cache misses through short instructions
Avoid the need for registers altogether

19. A key advantage of RISC over CISC for pipelining is:

RISC instructions are more feature-rich
RISC has fixed-length simple instructions, making pipeline stages uniform and easier to implement
RISC eliminates all data hazards
RISC supports more memory addressing modes

20. In a load-store ISA (typical of RISC), memory access is:

Allowed in all arithmetic and logical instructions
Restricted to dedicated LOAD and STORE instructions only
Not supported; all data stays in registers permanently
Combined with ALU operations in the same instruction

21. What is the primary goal of pipelining in a CPU?

To reduce the number of registers needed
To decrease power consumption
To increase instruction throughput by overlapping stages of multiple instructions
To eliminate the need for a cache

22. In a 5-stage pipeline (IF, ID, EX, MEM, WB), what is the ideal throughput for instructions?

One instruction every 5 cycles
One instruction every cycle (after the pipeline is filled)
Five instructions every cycle
One instruction every 3 cycles

23. Average Memory Access Time (AMAT) for a cache with hit time h, miss rate m, and miss penalty p is:

h + m × p
h × m + p
(h + p) / m
h / (1 – m) + p

24. Virtual memory allows a program to use an address space that is:

Exactly equal to the physical RAM installed
Potentially larger than the physical RAM available
Limited to the size of the CPU registers
Fixed at 4 KB regardless of hardware

25. A TLB (Translation Lookaside Buffer) is used to speed up:

Disk I/O operations
Virtual-to-physical address translation
Cache line replacement decisions
Floating-point arithmetic

26. A ‘page fault’ occurs when:

The CPU accesses a register that doesn’t exist
A required page is not currently in physical RAM and must be fetched from disk
The page table entry is marked as present
The TLB is full and cannot store more entries

27. ‘Thrashing’ in virtual memory systems refers to:

Excessive TLB misses causing slow address translation
Rapid, excessive page faults causing the CPU to spend most time swapping pages rather than executing
Cache lines being frequently replaced due to conflict misses
A program using more registers than available

28. Belady’s Anomaly is observed in which page replacement algorithm?

LRU
Optimal (OPT)
FIFO
Clock / Second-Chance

29. The Optimal (OPT / Belady’s Optimal) page replacement algorithm replaces the page:

That was used least recently
That was brought in first
That will not be used for the longest time in the future
That has the lowest reference count

30. DMA (Direct Memory Access) is primarily used to:

Allow the CPU to bypass cache during I/O
Transfer large blocks of data between I/O devices and memory without continuous CPU involvement
Enable multiple CPUs to share a single memory bus
Accelerate floating-point calculations in the ALU